In portable battery operated products such as a radio frequency communication device, it is desirable to have the lowest possible overall current drain in order to maximize battery life. Moreover, it is desirable to operate such products at the lowest possible voltage so as to minimize their total power consumption.
Conventional radio frequency communication devices may use one or more phase lock loops to synthesize frequencies needed for digital logic or radio frequency circuits. To conserve power, the synthesizers may be operated in a power saving mode where one or more of the phase lock loops are switched on during signal transmission or reception, and off during "sleep" periods. Operation in this fashion can substantially increase available battery life, thus resulting in more usable "talk time" in radio frequency communication devices such as cellular telephones or the like.
Power saving operation as discussed above is not without its problems. A major problem that confronts designers of power saving systems is that when switching a conventional phase locked frequency synthesizer from on to off, the tuning voltage developed inside the loop will decay. As a result of the decayed voltage, the frequency synthesizer's voltage controlled oscillator starts up at a frequency different from the desired operating frequency. Additionally, decay of the tuning voltage causes increased loop startup time and degraded frequency settling characteristics. Many artisans have attempted to solve the voltage decay problem using various techniques, one of the more successful of which is illustrated below.
A conventional microcomputer is used to implement a control program that controls an analog to digital converter for sampling the last operational tuning voltage developed inside the phase lock loop, then to apply a digital to analog converter voltage that is substantially equal to the last operational tuning voltage to the tuning element when re-activating the phase locked frequency synthesizer. This technique is generally successful in re-activating the phase locked frequency synthesizer at approximately the same output frequency. However, the complex circuits required in this approach may actually consume more power than is saved by operating the phase locked frequency synthesizer in a power saving mode. Consequently, prior attempts such as discussed above, have resulted in systems that more than eliminated any power saving and performance advantages gained through the use of sleep periods.
Thus, what is needed is voltage track and hold system that tracks a phase lock loop tuning voltage in a radio frequency communication device while operating in a power saving mode, the voltage track and hold system effectively conserving power while offering improved phase lock loop frequency switching, locking, and tracking characteristics.